We are hiring for one of our reputed clients for the following position. If you're interested and your experience matches the requirement, we'd love to hear from you.
Position: Verification Engineer
Experience: 1-5 Years
Location: Chennai
Contract tenure: 1 year
:
- Perform functional and compliance verification of PCIe-based SystemC IPs and subsystems.
- Integrate SystemC PCIe IP/Subsystem in Avery PCIe VIPs and utilize for protocol-level verification.
- Debug complex issues across transaction, data link, and physical layers of PCIe.
- Analyze and interpret PCIe specifications for test planning and coverage.
- Work closely with design, architecture, and validation teams to ensure feature completeness and spec compliance.
- Generate and review verification plans, test reports, and coverage metrics.
Required Skills:
- Strong hands-on experience with Avery PCIe VIP (integration, debug, customization).
- In-depth knowledge of PCIe protocol (Gen6 or higher).
- Solid experience in SystemVerilog / UVM methodology.
- Strong debug and problem-solving skills using simulators like Questa, VCS, or Xcelium.
- Familiarity with coverage-driven verification and constraint random testing.
- Good understanding of verification flow, regression setup, and scripting (Python/Perl/Shell).
- Excellent communication skills and ability to work independently in a rapid-paced environment.
Qualification:
- B.E/M.E/M.Tech or B.S/M.S in EE/CE
- Experience Level:5 years+