Job Summary

We are seeking an experienced Memory Layout Engineer to work on advanced semiconductor technologies including TSMC/Samsung 2nm, 3nm, 5nm, 7nm, and GlobalFoundries (GF) nodes. The ideal candidate will have strong expertise in custom memory layout, physical verification, and memory integration for high-performance SRAM/DRAM compiler IPs.

You will collaborate with Circuit Design, Physical Design, Verification, PDK, and Methodology teams to deliver optimized, manufacturable, and silicon-ready memory layouts.

Key Responsibilities

- Develop custom layouts for memory blocks including control logic, sense amplifiers, I/O blocks, bit cell arrays, row/column decoders, and peripheral circuits.
- Perform top-level memory integration for SRAM/DRAM compiler IPs.
- Execute and resolve DRC, LVS, Density, ERC, and Physical Verification issues.
- Optimize layouts for area, power, performance, yield, and manufacturability.
- Address IR Drop and Electromigration (EM) challenges in memory layouts.
- Work closely with Circuit Design teams to ensure layout matches design intent.
- Ensure compliance with advanced technology node design rules and DFM guidelines.
- Collaborate with PDK and Methodology teams for process updates and layout improvements.
- Support layout sign off and tape-out activities.

Required Skills

- 4–8 years of experience in Memory Layout for ASIC/VLSI designs.




- Hands-on experience in layout of:
- Sense Amplifiers
- Control Logic
- Bitcell Arrays
- Row/Column Decoders
- I/O Blocks
- Memory Peripheral Circuits
- Robust understanding of SRAM, DRAM, and Memory Compiler IPs.
- Experience with Top-Level Memory Integration.
- Expertise in:
- DRC
- LVS
- Density Verification
- Physical Verification
- Physical Closure
- Knowledge of IR Drop and Electromigration (EM) analysis.
- Experience with advanced technology nodes:
- TSMC/Samsung – 2nm, 3nm, 5nm, 7nm
- GlobalFoundries (GF) technologies
- Proficiency with Cadence and/or Synopsys layout tools.
- Experience using Mentor Graphics, Cadence, or Synopsys physical verification tools.
- Strong understanding of FinFET technology and advanced node design rules.
- Knowledge of Design for Manufacturability (DFM) guidelines.
- Good understanding of memory architecture and bit cell layout concepts.

Preferred Skills

- Experience with advanced custom layout methodologies.
- Exposure to ultra-deep sub-micron process technologies.
- Understanding of reliability and yield optimization techniques.
- Experience supporting silicon bring-up and post-layout debug.
- Strong analytical and debugging skills.
- Excellent communication and collaboration abilities.

Pay: ₹1,000,000.00 - ₹1,800,000.00 per year

Work Location: In person

📌 Memory Layout Engineer (India)
🏢 Spatial Alphabet
📍 India