- 10 years with expertise in full-chip timing closure
Key Responsibilities :
- Lead full-chip static timing analysis and drive timing signoff for complex SoC designs
- Develop advanced timing methodologies incorporating AOCV, POCV, and statistical timing analysis
- Mentor timing engineers on advanced STA techniques, debugging strategies, and tool usage
- Interface with design, synthesis, and physical implementation teams to resolve timing challenges
- Conduct multi-voltage domain analysis and ensure proper timing across voltage level shifters
- Establish timing quality metrics and implement continuous improvement initiatives
- Evaluate current timing analysis tools and methodologies for improved accuracy and efficiency
- Lead timing aspects of design reviews, tapeout readiness assessments, and post-silicon correlation
📌 Static Timing Analysis Lead (India)
🏢 CAREER MAKERS
📍 India
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