Role Overview

We are hiring a Staff DFT Engineer to lead DFT strategy, architecture, and implementation for complex, high-performance SoCs. You will define methodologies, and drive DFT from RTL to silicon bring-up, ensuring optimal quality, cost, and time-to-market. What You’ll Do

Define DFT architecture and test strategy for SoCs, including scan, compression, MBIST, LBIST, and IO test.

Lead ATPG pattern generation, optimization, and diagnosis flows across multiple fault models.

Architect and oversee MBIST, BISR, and memory repair solutions for large memory arrays.

Design and implement advanced test access mechanisms using JTAG, Boundary Scan (BSCAN), and IJTAG (IEEE 1687).

Drive DFT timing closure, power-aware DFT, and hierarchical/multi-core test strategies.

Own pre-silicon DFT verification (ATPG simulation, GLS) and coverage closure.

Lead silicon bring-up, ATE test program development, post-silicon validation, debug, and yield improvement.

Collaborate with cross-functional teams to integrate DFT into the overall design flow and resolve complex issues.





Mentor junior and mid-level engineers; contribute to methodology development and tool evaluation.

Optimize test time, data volume, and manufacturing test costs.

What We’re Looking For Bachelor’s/master’s degree in Electronics/Electrical Engineering.

8+ years of strong hands-on experience in DFT for complex SoC/ASIC projects.

Expert-level knowledge of ATPG, MBIST, LBIST, IJTAG, BSCAN, scan compression, and related areas.

Proven track record in silicon bring-up, ATE support, and post-silicon debug.

Deep understanding of full ASIC flow (RTL to Silicon) and DFT impact on PPA.

Proficiency with leading EDA tools (Synopsys TetraMAX/DFTMAX, Siemens/Tessent SSN, TestKompress etc.).

Solid scripting and automation skills.

Good To Have

Knowledge of advanced topics like 2.5D/3D packaging test, analog/mixed-signal DFT. Job Location

Hybrid/ On-site - Bangalore / Remote - India

📌 Staff DFT Engineer (Bengaluru)
🏢 tylsemi
📍 Bengaluru