Role: Senior Power Integrity Engineer

Function: Hardware Engineering / Signal & Power Integrity

Location: Bengaluru, India

Type: Full-time

Industry: Telecommunications, Semiconductors, Information Technology & Services

About Company The company targets the high-growth AI data center infrastructure market. It designs, manufactures, and sells photonic interconnect solutions — including pluggable, near-packaged, and co-packaged optics built for modern AI architectures.

The company uses in-house custom robotics and AI-optimized manufacturing to drive high yield and rapid innovation. It is backed by top-tier investors including Mayfield and Spark Capital, and led by veterans from Cisco, Juniper, Meta, Lumentum, and Coherent.

The team of ~120 is hands-on, cooperative, and deeply mission-driven across optics, silicon, and networking. As a well-funded Series C startup, there is still ample opportunity to shape the product and culture from the ground up.

Position Overview

This role owns power distribution network (PDN) design and optimization for OSFP transceiver modules operating at 800G and beyond. The engineer will drive PI simulation, lab validation, and cross-functional co-optimization to ensure robust, low-noise power delivery across high-speed silicon photonics, DSPs, and retimers — directly impacting the reliability and performance of the company's next-generation photonic interconnect products deployed in hyperscale AI data centers.

Role & Responsibilities

- Run PI simulations using Ansys SIwave, Keysight ADS, or Cadence Sigrity to model and optimize PDN for OSFP modules, targeting <1mΩ impedance across 10kHz–100MHz bandwidth.
- Analyze and mitigate power rail decoupling, VRM placement, and bypass capacitor strategies for multi-rail supplies (0.8V core, 1.8V I/O, 3.3V aux) in high-current designs up to 100W .
- Collaborate on PCB stackup design,



via optimization, and plane splitting to reduce simultaneous switching noise (SSN) and ground bounce in 112G PAM4 SerDes environments.
- Validate designs through lab measurements using VNA, oscilloscopes, and power analyzers; correlate simulation results with hardware prototype behavior.
- Support signal integrity co-optimization, thermal-PDN synergy (TIM integration), and compliance to IEEE 802.3ck/802.3df standards.
- Author PI reports, lead design reviews, and mentor junior engineers on PDN best practices for hyperscale OSFP deployments.

Must Have Criteria

- Bachelor's or Master's in Electrical/Electronics Engineering with a focus on RF or mixed-signal design.
- 8–10 years of hands-on PI experience for high-speed transceivers (OSFP, QSFP-DD, or CDFP) with 50G SerDes.
- Proficiency in PI simulation tools — Ansys SIwave, HyperLynx, or Cadence Sigrity.
- Scripting experience in Python or MATLAB for simulation automation and data analysis.
- Strong working knowledge of power converter topologies (Buck/Buck-Boost), ESL modeling, and EMI/EMC mitigation techniques.
- Experience with OSFP mechanical constraints, flex-rigid PCBs, and multi-die integration.

Nice to Have

- Familiarity with thermal co-simulation (e.g., Ansys Icepak integration) for heat-affected PDN performance.
- Knowledge of advanced PCB materials — low-Dk dielectrics or embedded passives — for PDN miniaturization.
- Prior hands-on work on 1.6T OSFP or Co-Packaged Optics (CPO) prototypes.

What We Offer

- Comprehensive benefits package including health insurance.
- Direct exposure to cutting-edge photonic interconnect technology shaping AI data center infrastructure.
- Professional development support and access to state-of-the-art simulation and lab environments.
- High-ownership role within a lean, expert team of industry veterans — with real influence over product and architecture decisions.

📌 Senior Power Integrity Engineer (Bengaluru)
🏢 Recrew AI
📍 Bengaluru