Project Description:

Working for a global provider of network test, monitoring and assurance solutions for telecommunications, cloud, enterprises, first responders, military, aerospace, and railway. VIAVI is also a leader in light management technologies for 3D sensing, anti-counterfeiting, consumer electronics, industrial, automotive, government and aerospace applications.

Employees working on this project are passionate about supporting customer success and we welcome people who bring their best every day to the company – to question, to collaborate and to push for solutions that will delight our customers.

Responsibilities:

We are seeking an enthusiastic and skilled Staff FPGA Engineer to join our team developing state of the art Communications Test & Measurement products.

The successful candidate will architect and implement high-speed FPGA designs, using Verilog/System Verilog/VHDL and cutting-edge simulation, synthesis, place and route, and verification tools.

Mandatory Skills Description:

BS or MS degree in Electrical and/or Computer Engineering and a minimum of 8 years relevant experience

High speed FPGA design experience using Verilog/SystemVerilog or VHDL required





Working knowledge of Ethernet from 10M to 1.6T, and IP protocol.

Working knowledge of VLANs, MPLS, VPLS, and Voice/Video over IP (VoIP, IPTV) strongly desired

Experience using AMD or Altera FPGA devices and implementation tools

Experience with FPGA components such as transceivers, hard IP, and PLLs strongly desired

Experience with optical interfaces and modules (SFPs, QSFPs) desired

Version control experience using Git or similar tools

Solid written and oral communication skills and the ability to communicate ideas with people from across the world

Exceptional analytical and organizational skills, coupled with a well-focused attention to detail; ability and commitment to produce a timely and highly accurate product

Nice-to-Have Skills Description:

General purpose microprocessor and DSP systems, PCIe, high-speed digital board design, PLL design, and analog signal conditioning experience a plus

Simulation experience using Siemens Questa, Aldec Riviera, or similar tools

Utilization of generative AI tools to assist in concept and implementation of FPGA designs

Languages:

English: B2 Upper Intermediate

📌 Senior FPGA Developer (India)
🏢 Luxoft
📍 India