- In depth knowledge of full custom (transistor level) CMOS VLSI circuit layout techniques.
- Ability to create high density, high performance CMOS layouts and understand tiled layout.
- Knowledge of CAD tools for IC layout, design rule checking and layout vs. schematic comparison (LVS).
- Experience using Cadence & Mentor digital / analog design tool suite, Simulators - Avant! H SPICE / Mentor ELDO simulator / NASDA HSIM & verification tools like Mentor Calibre & Cadence Dracula. Knowledge in developing behavioral models for design sub-blocks / digital circuits.
- Min Educational Requirements BS in EE. MS in EE preferred.
- Email your resume to [email protected] with Job Code – DE in the subject line.
📌 Circuit Design (India)
🏢 Perfectus Technology
📍 India
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