Job Title-RTL Verification Engineer

Experience-310 Years

Location-Bangalore / Noida / Hyderabad

Employment Type-Full Time

Job Summary

We are seeking an experienced RTL Verification Engineer to verify complex ASIC/SoC designs using SystemVerilog and UVM methodology. The candidate should have robust debugging skills and hands-on experience in verification environments, functional coverage, assertions, and protocol verification.

Key Responsibilities

- Develop UVM/SystemVerilog based verification environments.
- Create reusable verification components.
- Write test plans based on design specifications.
- Develop directed and constrained-random test cases.
- Perform functional verification of RTL blocks.
- Debug simulation failures.
- Develop assertions (SVA).
- Perform code coverage and functional coverage analysis.
- Execute regression testing.
- Identify and close coverage gaps.
- Collaborate with RTL Design, Architecture, DFT, and Physical Design teams.
- Verify industry-standard protocols.

Required Skills

- SystemVerilog
- UVM




- Verilog
- Assertions (SVA)
- Functional Verification
- Constrained Random Verification
- Coverage Driven Verification
- Code Coverage
- Functional Coverage
- Regression Testing
- Debugging Skills
- Simulation Concepts
- Digital Design Fundamentals
- FSM Verification
- CDC Verification
- Lint Awareness
- Protocol Experience

Experience in one or more:

- AXI
- AHB
- APB
- PCIe
- USB
- Ethernet
- DDR
- MIPI
- SPI
- I2C
- UART
- Preferred Tools
- QuestaSim
- VCS
- Xcelium
- Verdi
- DVE
- SimVision
- SpyGlass
- JasperGold (Preferred)
- VC Formal (Preferred)
- TCL
- Python
- Perl
- Git
- Jenkins

Qualifications

- B.E./B.Tech/M.E./M.Tech in
- Electronics
- ECE
- EEE
- VLSI
- Microelectronics

Good to Have

- Formal Verification
- Emulation
- FPGA Validation
- Low Power Verification (UPF)
- Scripting using Python/TCL/Shell
- CI/CD exposure

📌 Rtl Verification Engineer (Bengaluru)
🏢 Qiskitq Technology
📍 Bengaluru