Job Title- Mid Level SoC Design Engineer ARM Architecture Location- Hyderabad TL Client- Product Based Role Overview We are seeking a Mid-Level SoC Design Engineer with strong expertise in ARM architecture and hands-on experience working with Arm Corestone reference systems The role involves supporting subsystem design integration and optimization activities across client s next-generation SoCs In addition we are looking for engineers with a solid background in ASIC SoC and RTL design with an emphasis on front-end ASIC design techniques and methodologies You will collaborate with architecture verification and physical design teams to bring complex ARM-based subsystems to production-quality readiness Key Responsibilities Design and integrate ARM-based subsystems derived from Arm Corestone reference packages into SoCs Implement and modify RTL for CPU subsystems AMBA interconnects memory controllers and peripheral IP Collaborate with architecture teams on feature definition microarchitecture updates and performance targets Work closely with verification teams to debug functional issues and ensure high-quality coverage closure Support synthesis timing analysis and physical design teams during SoC execution Drive documentation design reviews and bring-up support for early silicon and emulation platforms Contribute to methodology improvements for subsystem integration and design scalability Required Qualifications Bachelor s or Master s degree in Electrical Engineering Computer Engineering or related field 6 8 years of experience in SoC or subsystem design Strong knowledge of ARM architecture AMBA protocols AXI AHB APB and system-level integration Hands-on experience with Arm Corestone-based packages or similar ARM reference designs Solid experience in ASIC front-end design including RTL development and integration flows Proficiency in Static Timing Analysis using Primetime or Cadence tools Experience in ASIC synthesis Clock Domain Crossing CDC Reset Domain Crossing RDC techniques using Spyglass Familiarity with low-power design techniques UPF and tools like PowerArtist or Power Compiler a plus FPGA prototyping experience is desirable Strong debugging skills across simulation lint CDC and synthesis environments Ability to collaborate in a fast-paced cross-functional engineering setting Preferred Qualifications Knowledge of low-power design techniques and clock power domain architecture Exposure to AI ML accelerator-based SoCs is a plus Familiarity with FPGA prototyping emulation platforms or early silicon bring-up Advanced degrees B Tech M Tech BE ME M Sc M S in Computer Science or Electronics Electrical Engineering Regards Anil Sheoran (phone hidden)