Job Title:IP Verification Engineer – UVM verification Exp Level:4+ yrs Location:Bangalore/Hyderabad :System Verilog based UVM Functional verification, Behavioral modelling of functional blocks. System level performance verification, traffic patterns, bandwidth & latency analysis. Expertise in AXI4 bus protocol.
Experience in Network On Chip (NOC) protocol.
Experience in multi-master, multi-slave AXI4 use-case configurations. Knowledge of DRAM memory controllers. Develop and execute testbenches to validate the functionality and correctness of models, as well as participate in system-level testing and debugging.
Basic Job
Deliverable:Setup verification workplace and bring up simulations with various simulations such as VCS / Questa / Xcellium / Riviera SV/UVM Functional verification Expertise in Vivado for simulation debugs Qualification:B.E/M.E/M.Tech Interested can Share CV to [email protected]
📌 Ip Verification Engineer (Yelahanka)
🏢 ACL Digital
📍 Yelahanka
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