Role & responsibilities

- Develop and maintain UVM-based verification environments/testbenches for SoC/IP-level designs
- Verify PCIe, AXI4, and LPDDR protocol interfaces against specification and design intent
- Write test plans, test sequences, and functional/code coverage models
- Debug simulation failures and collaborate with RTL design teams to resolve issues
- Develop and integrate SystemVerilog Assertions (SVA) for protocol compliance checking
- Work with Verification IPs (VIPs) for PCIe/AXI4/LPDDR interfaces
- Drive functional coverage closure and regression management
- Document verification plans, results, and closure reports

Preferred candidate profile

- 5-8 years of hands-on experience in ASIC/SoC functional verification
- Solid expertise in SystemVerilog and UVM methodology
- Proven experience verifying PCIe, AXI4, and LPDDR protocols
- Experience with industry-standard simulators (VCS, Questa, or Xcelium)
- Familiarity with VIPs (Synopsys/Cadence) for the above protocols
- Scripting skills in Perl/Python/TCL for verification automation
- Strong understanding of digital design fundamentals and SoC architecture

📌 SV-UVM Verification Engineer PCIe // LPDDR (Telangana)
🏢 Accelyzei
📍 Telangana