- Top 3 Skills: 6+ years of experience in ASIC/SoC Physical Design with solid exposure to Full-Chip Floorplanning.
- Hands-on experience with industry-standard physical design tools such as ICC2, Fusion Compiler, or Innovus.
- Solid understanding of floorplanning concepts, hierarchy integration, pin planning, and routing architecture.
- Proficiency in scripting is a plus.
KEY RESPONSIBILITIES:
- Drive full chip floorplanning activities for complex SoC designs.
- Perform pin planning and pin placement to achieve optimal routing convergence.
- Plan and implement feed-through insertion strategies to improve signal connectivity across chip tiles.
- Plan and insert repeaters for long-distance signal paths to meet timing and signal integrity requirements.
- Implement Source Synchronous Bus (SSB) planning, including bus topology analysis, physical implementation strategy, and routing feasibility assessment.
- Physical DRVs need to be fixed after pin/feed implementation.
- Collaborate closely with RTL,
physical design, timing, and implementation teams to ensure seamless full-chip integration
PREFERRED EXPERIENCE:
- 6+ years of experience in ASIC/SoC Physical Design with strong exposure to Full-Chip Floorplanning.
- Solid understanding of floorplanning concepts, hierarchy integration, pin planning, and routing architecture.
- Experience with feed-through planning and repeater insertion methodologies.
- Knowledge of congestion analysis, timing-aware floorplanning, and physical design methodologies.
- Hands-on experience with industry-standard physical design tools such as ICC2, Fusion Compiler, or Innovus.
- Proficiency in Tcl, Python, or Shell scripting is a plus.
Interview Mode:
- Round of interviews: 2
- R1: F2F
- R2: F2F(Both interviews will happen on the same day)
Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.