Role description

- FPGA Validation

JD:-

FPGA validation engineers with experience in PCIe 4/5, DDR 4/5 or USB3 and Serdes.

- Hands on experience working with DSO and Logic Analyzers

- Leads and senior members need board level debugging knowledge

- Some of the team members should be proficient with embedded c and RTL coding.

- Basic knowledge on ARM Cortex-M3 or Risc-V will be helpful

Skills

vlsi design,fpga engineering,embedded c,serdes,

About UST
UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.

📌 Technical Lead I - VLSI (India)
🏢 UST
📍 India