At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Responsibilities

- Design Verification for interconnect IP
- Relevant experience in interconnect and subsystems is strongly preferred
- Crafting verification plans and executing on those plans to verify highly complex and configurable designs.
- Responsible for coverage collection and closure
- Work closely with cross functional teams (DV/Arch/Design/FW) to identify coverage scope

Required Skills and Experience:

- 8+ years of design verification experience
- BS (or higher) in EE/Computer Engineering
- Strong technical and interpersonal skills
- Excellent knowledge of Interconnects, NoCs and design verification fundamentals.
- Thorough understanding of System Verilog, UVM, and other programming languages to build adaptable and reusable complex testbenches
- Experience with development of fully automated flows
- Exposure to scripting languages like Perl, Unix shell or similar languages
- Experience with Formal Verification will be a plus
- Experience with Gate Level Simulations
- Excellent written and oral communication skills necessary

We’re doing work that matters. Help us solve what others can’t.

📌 Principal Design Engineer (India)
🏢 Cadence Design Systems
📍 India