We're looking for an experienced Design Verification (DV) Solution Architect to define and lead SoC and subsystem verification strategies. The role involves driving verification closure from specification through tapeout, building scalable verification methodologies, and leading complex SoC verification programs. Requirements
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Mandatory
Skills
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âœ”ï¸ 12+ years of Design Verification experience
âœ”ï¸ Solid SoC-Level DV Experience (Mandatory)
âœ”ï¸ Experience leading multiple SoC verification programs through tapeout
âœ”ï¸ Expertise in UVM, SystemVerilog, and Assertions