As a member of AMD, you will help bring to life cutting-edge designs. As a member of the DFT team, you will work closely with the DFT Architecture, IP design, Physical Design teams, and Product Engineers to achieve first pass silicon success.
The Person
The candidate will be highly accurate and detail-oriented, possessing valuable communication and problem-solving skills.
Key Responsibilities
- Strong understanding of Scan Architecture and Scan features.
- Scan insertion and ATPG pattern generation for Stuck-at, Transition ATPG, IDDQ Pattern Generation.
- GLS, timing, and power-aware simulations.
- Test coverage and test cost reduction analysis.
- Yield analysis and debugging for design root cause and recovery.
- Post silicon bring up: planning, co-ordination, and execution.
- DFT silicon bring up expertise from across tech various nodes.
- Extensive silicon debugging for phasing closure and production enablement.
- Experience with multiple SoC tape-outs and post-silicon bring-ups.
Preferred Experience
- Experience with Mentor TestKompress and/or Synopsys Tetramax/DFTMAX.
- Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design.
Academic Credentials
- Bachelor's or master's degree in Electronics/VLSI/Electrical Engineering.