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The job is for an experienced ASIC design engineer with strong technical skills in Verilog/SystemVerilog RTL design, CDC, and Lint. The ideal candidate will have experience in micro-architecture, integration, and debugging, as well as exposure to synthesis, timing, and low-power design. The role requires team leadership and cross-functional collaboration skills.

Key Responsibilities :

- Strong ASIC RTL design skills in Verilog/SystemVerilog
- Experience in micro-architecture, integration, and debugging
- Exposure to synthesis, timing, and low-power design
- Team leadership and cross-functional collaboration skills

Required Skills :

- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
- Robust expertise in Verilog/SystemVerilog RTL design
- Experience in CDC/Lint closure, synthesis, and timing analysis
- Knowledge of low-power techniques, including UPF and clock gating

📌 ASIC RTL Design Lead Engineer (India)
🏢 Ayno Technologies
📍 India