At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Position Description:

- IP Integration and release Engineer for SSG IP Release engineering team.
- Position is based in Bangalore.
- The role would include IP integration, verification, and release of the IP solution of Cadence to different customers.
- The work involved will be working with the existing RTL, integration of the PHY and controller to create the sub-system, addition of new features into the RTL, ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring design is clean for LINT and CDC design guidelines.
- Proficient in ASIC development flows like Lint/CDC/Synthesis (preferably with Genus)/STA. Ability to debug and setup new flows.

Position Requirements:





- BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design verification engineer, with a large portion of the recent work experience on RTL integration and verification.
- 6-10 years of core RTL integration and verification experience using Verilog is a must.

- System Verilog experience and experience with UVM based setting usage / debugging is required.
- PCIe/CXL/IDE experience is highly desirable. Prior experience in implementation of complex protocols is a must.
- Prior experience in IP development teams would be an added advantage.

Scripting knowledge is an advantage.

We’re doing work that matters. Help us solve what others can’t.

📌 Lead Design Engineer (India)
🏢 Cadence Design Systems
📍 India