- ASIC
- Location: Bangalore
- Experience: 3 - 5 Years
Required Skills & Knowledge:
- B. Tech / M. Tech with hands on experience into Physical verification at block-level& chip-level.
- DRC, LVS DFM, Antenna, Density Fill Routines and other Tape-out sign-off experience is a must.
- Experience using Synopsys ICC Tool.
- Tape-out experience of multiple complex chips at 14 nm or below is required.
- Experience with Mentor Calibre or Synopsys ICC and ICV is a must.
- Programming experience in tcl, Perl or C.
- Proficient in planning for and addressing electrical considerations throughout the design process (EM, IR, Noise, etc.).
- Physical verification flow automation exposure will be an added advantage.
To learn more about Siliciom Technologies, please contact us at
[email protected]
📌 Physical Verification Engineer: (India)
🏢 Siliciom Technologies
📍 India