- Experience level: 5+ Years.
- Work Experience in Synthesis Constraints development, LINT checks, CDC checks
- Experience in working/leading full-chip STA closure, defining mode requirements and corners for timing closure.
- Experience in Formal Verification with Synopsys Formality and / or Cadence Conformal LEC.
- Chip-level constraint development and constraint validation.
- Solid knowledge of clock tree synthesis, SI analysis.
- Strong understanding of ECO cycle .
Designation: Senior Synthesis/STA Engineer
Experience: 4+ years
Location: Bangalore/Hyderabad/US
Qualification: Bachelor/Master’s Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics
Number of Positions: 5
📌 Senior Synthesis/STA Engineer (India)
🏢 pozibility technologies
📍 India
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