Engineer Trainee (India)

Engineer Trainee (India)

03 Aug
|
SmartDV Technologies
|
India

03 Aug

SmartDV Technologies

India

- B.E or MTech from reputed university with 0-2 years experience.
- Strong understanding of Digital design
- Working experience with Verilog or VHDL or SystemVerilog
- Experience in writing C or C++
- Understanding of OOPS.
- Knowledge of Perl or Python or TCL scripting languages
- Very positive academic track record

Send resumes to [email protected]

📌 Engineer Trainee (India)
🏢 SmartDV Technologies
📍 India

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