Company:
Qualcomm India Private Limited
Job Area:
Engineering Group, Engineering Group > Hardware Engineering
General Summary:
The responsibility includes:-.
-Independent planning and execution of Netlist-to-GDSII.
-Valuable understanding of basics of static timing analysis.
-Well versed with the Block level and SOC level timing closure (STA) methodologies, ECO generation and predictable convergence.
-Should be able work in close collaboration with design, DFT and PNR team and resolve issues wrt constraints validation, verification, STA, Physical design, etc.
-Should have good exposure to high frequency multi voltage design convergence.
-Good understanding of clock networks.
-Circuit level comprehension of timing critical paths in the design; Understanding of deep sub-micron design problems and solutions (Skew analysis, clock divergence, signal integrity, DFM etc.)
-Work independently in the areas of RTL to GDSII implementation;
-Well versed with Tcl/Perl scripting; willing to handle technical deliverables with a small team of engineers.
-Strong problem-solving skills and communication skills.
-Full exposure to all aspects of design flows like floor-planning, placement, CTS, routing, crosstalk avoidance, physical verification.
Experience in leading block level or chip level Timing closure & Physical Design activities
Minimum Qualifications:
• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
-Masters/Bachelors Degree in




Electrical/Electronics
science engineering with at least 2-15+ yrs of experience
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📌 Physical Design Engineer (215 Years Experience) (Chennai)
🏢 Qualcomm
📍 Chennai