Are you passionate about driving performance at the silicon level? We are looking for an experienced
STA Engineer
with 5+ years of expertise in Static Timing Analysis (STA) to join our team!
Key Responsibilities:
Perform timing analysis, validation, and debug across multiple PVT corners using
Tempus
Hands-on experience with
Tempus DMMMC
flow for STA
Handle STA setup, convergence, reviews, and signoff for both
scan and functional modes
Review unconstrained endpoints and analyze detailed timing reports
Deep understanding of
noise, crosstalk, and OCV effects
Experience with
block-level and full-chip timing closure
at advanced nodes like
22nm, 16nm, 5nm
Collaborate with cross-functional teams (design, synthesis, PnR) for smooth closure
Scripting knowledge in
TCL
and
Python
Prior experience with
ADI/Cadence flows
and
power domain-based designs
is a plus
📌 Sta Engineer (Bengaluru)
🏢 Zealogics.com
📍 Bengaluru
Reply to this offer
Impress this employer describing Your skills and abilities, fill out the form below and leave Your personal touch in the presentation letter.