DFT Engineers

Location: Bangalore
Experience: 8–15 Years
Work Mode: Work From Office

We are looking for experienced DFT (Design for Test) Engineers to join our growing semiconductor team. If you have robust expertise in DFT architecture, scan insertion, ATPG, MBIST, LBIST, and IJTAG, we'd love to hear from you.

Key ResponsibilitiesRTL DFT Implementation

- Perform RTL DFT insertion and verification.
- Implement and validate SSN (Streaming Scan Network).
- Execute IJTAG (IEEE 1687) insertion and verification at Block and SoC level.
- Perform MBIST insertion, memory repair configuration, and verification at Block and SoC level.
- Implement and validate EDT-based scan compression.

Netlist DFT & ATPG

- Perform netlist DFT insertions and pattern verification.
- Execute gate-level scan stitching and DRC checks.
- Implement and validate LBIST architecture.
- Generate ATPG patterns for Stuck-at and Transition fault models.
- Perform Gate-Level Simulation (GLS) for pattern validation.
- Analyze coverage, debug pattern issues, and optimize test coverage.





Required Skills

- Strong experience in RTL and Netlist DFT flow.
- Hands-on expertise in Scan Insertion, Scan Compression (EDT), MBIST, LBIST, and IJTAG (IEEE 1687).
- Experience with ATPG pattern generation, GLS simulations, and coverage analysis.
- Good understanding of SoC/ASIC design flow and DFT methodologies.
- Excellent debugging and problem-solving skills.

Preferred

- Experience in Block and SoC-level DFT implementation.
- Strong communication and collaboration skills.
- Ability to work with cross-functional Design, Verification, and Physical Design teams.

If you're passionate about semiconductor design and testing and are looking for your next career prospect, we'd love to connect with you.

Apply Now!

Pay: From ₹1,000,000.00 per year

Benefits:

- Flexible schedule
- Health insurance
- Life insurance
- Paid sick time
- Paid time off

Work Location: In person

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