Bangalore, Karnataka
Job Summary
IC Package Design Engineer with 8+ years experienced

Experience with Cadence Advanced Package designer, IC Package Design experience with Cadence APD Layout tool
Good understanding of package/substrate design and package assembly rules related to flip chip designs.
Good knowledge and experience in BGA ball map assignment and Die bump analysis for routability.
Already done 4 to 5 tape outs.

Exposure to different package technologies such as MCM, flip chip / wire bond, 3D, 2.5D etc., added advantage
Expertise in High-Speed Complex Package and PCB designs with HDI, Blind and Buried Via technologies.
Experience with PDN, SI/PI requirements of package layout.

Hands-on expertise with Package designs involving High Speed Parallel Bus interfaces including DDR, LPDDR, GDDR and HSIO interfaces including PCIe, SERDES.
Valuable Exposure to Stackup design, DFM, DFA rules and adherence.
Should have expertise in constraint setting in APD layout tool.

Key Responsibilities
1.



To design and architect large-scale solutions, ensuring scalability, performance, and security.
2. To train and develop team so as to ensure that there is an adequate supply of trained manpower in the said technology and delivery risks are mitigated.
3. To continuously upskill with cutting-edge tech to deliver high-quality, future-proof solutions meeting client expectations and industry standards.
4. To leverage domain/tech expertise to gather client needs, deliver solutions, and craft a technology strategy aligned with business goals.

Skill Requirements

IC Package Design, Flip Chip, FcBGA, MLO design, MLC design, 2.5D, 3D design experience, Cadence APD

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📌 Senior Technical Architect (India)
🏢 HCLTech
📍 India