- Strong in digital IP design using RTL for lower technology nodes [3/4/7nm].
- Experience in micro architect and implementation of complex IP blocks for high-speed designs.
- Optimization of digital logic by analysing timing reports at various stages of ASIC design cycles and defining solutions for path.
- Experience in developing modules for AXI4/5, CHI interfaces.
- Experience in RTL implementation of PCIe/CXL transaction layer or AXI bridging layer.
- Experience in the closure of RTL blocks with quality checks, CDC/RDC/Lint.
- Define and propose innovative solutions to the problem.
- Valuable team player, proactive in communications, lead proposed solutions to closure.
- Documentation on design approaches, discuss it within the team, come up with conclusive approaches and drive it.
- Co-work with other functional teams on project requirements.
Experience (years) : 4+ years
Education Qualification:
BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or related field