This is a full-time on-site role for a Sr Principal Physical Design Engineer based in Bengaluru. The engineer will be responsible for overseeing and contributing to the complex Design IP's like Memory IP's, Ser Des & D2D IP's with higher frequencies on the latest technology nodes..

Day-to-day tasks include floorplanning, placement, clock tree synthesis, routing, and physical verification. The role also involves collaborating with cross-functional teams, mentoring junior engineers, and ensuring design meets performance, power, and area specifications.

Qualification

- Solid expertise in floorplanning, placement, clock tree synthesis, routing, and physical verification
- Experience with physical design tools like Cadence Innovus, Synopsys ICC2, or similar
- Proficient in scripting languages such as TCL, Perl, and Python for design automation
- Knowledge of timing analysis, signal integrity, and power analysis
- Excellent problem-solving skills and attention to detail
- Strong communication and collaborative skill
- Bachelor’s or Master’s degree in Electrical Engineering or related field
- 11-15 years of relevant experience in physical design
- Experience in leading and mentoring a team

📌 Lead Semiconductor Layout Engineer (Bengaluru)
🏢 Cadence System Design and Analysis
📍 Bengaluru