Key Responsibilities:

· Lead and manage RTL design activities for complex ASICs, ensuring high performance and low power consumption.

· Integrating RTL components into System-on-Chip (SoC) designs Integrating RTL components into System-on-Chip (SoC) designs

· Architect and implement RTL for digital circuits (such as processors, communication systems, or custom IP cores).

· Mentor and guide junior RTL engineers in best practices for design, coding standards, and optimization techniques.

· Develop and refine RTL code in Verilog/SystemVerilog for ASIC development.

· Collaborate with cross-functional teams (Verification, Physical Design, and Software) to ensure successful integration of the ASIC design.

· Perform RTL design reviews, debugging, and optimization to meet design targets such as area, speed, and power.

· Work on creating micro-architectural specifications and ensure the design meets project requirements.

· Ensure designs are implemented with proper synchronization, timing constraints, and low power techniques.

· Participate in top-level design, integrating IP blocks, ensuring design consistency across subsystems.

· Drive the design flow from architecture and specifications through to implementation.





· Prepare and maintain technical documentation for designs and related processes.

· CDC, LINT and Integration expertise is expected.

Required Skills & Experience:

· Bachelor's, Master's, or PhD in Electrical Engineering or related fields.

· 5 to 9 years of experience in RTL design for ASICs.

· Work Location is Bangalore.

· Expertise in RTL design using Verilog or System Verilog.

· Solid understanding of digital design principles, including timing analysis, state machines, and pipelining.

· In-depth knowledge of ASIC design flow, from RTL to tape-out.

· Experience with EDA tools for synthesis, simulation, and timing analysis (e.g., Synopsys, Cadence).

· Robust debugging and problem-solving skills.

· Good knowledge on scripting (Python, Perl and Shell scripting)

· Knowledge of power, performance, and area (PPA) optimization techniques.

· Experience with designing for low-power, high-speed circuits is highly desirable.

· Excellent communication skills and the ability to work in a team environment.

Perks and benefits

As per company norms

Work Location: In person

📌 ASIC RTL Design Engineer (India)
🏢 Sauvira Solutions Private
📍 India