Job Requirements

Role Overview

In this role, you will be responsible for the end-to-end physical implementation of complex blocks and full-chip SoCs. You will work closely with synthesis, architecture, and signoff teams to transform synthesized netlists into clean, manufacturing-ready GDSII/OASIS layouts while overcoming challenging routing, timing, and power constraints.

Key Responsibilities

- Design Implementation: Drive complete physical design flows using Cadence Innovus, taking designs from netlist/floorplan all the way to tape-out.
- Floorplanning & Power Planning: Execute robust floorplans, pin assignments, power rings, and stripes that meet macro and standard cell utilization limits.
- Clock Tree Synthesis (CTS): Develop and optimize clock distribution networks using ccopt to minimize skew, latency,



and power while meeting latency targets.
- Timing & Optimization: Perform pre- and post-route timing closure (setup/hold) and DRV fixes, utilizing Innovus super-commands and ECO generation.
- Signoff Compliance: Ensure designs pass DRC, LVS, and antenna rules, as well as electromigration and IR (EMIR) drop limits.
- Scripting: Develop and refine TCL scripts and automated flows within the Innovus workplace for efficiency and regression testing.

Required Qualifications

- Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

📌 PD Innovus Engineer (India)
🏢 Quest Global
📍 India