Role description

: Must solid experience with memory technologies, and a desire to develop broader exposure to their downstream use in a energetic, cutting edge VLSI Synthesis environment. This role will provide key support for multiple projects in a globally distributed team. Responsibilities will include: Read and understand documentation of and answer end-user question regarding Synopsys memory compilers Generate compiled memory views and perform quality assurance on those views for each released version. Perform program management, tracking action items and progress against due dates. EXPERIENCE AND EDUCATION:Understanding of SRAMs and memory compilers (Synopsis Memory Compiler experience preferred) as well as VLSI design flow;Familiarity with memory design and views of memories, e.g. Verilog, timing (.lib), LEF, GDS;Familiarity with physical design verification, e.g. DRC and LVS;Able to perform and interpret circuit simulations, e.g.



using SPICE;Ability to execute and modify scripts in PERL, Unix shell, Tcl, Python or related language

Skills

vlsi design,vlsi,memory compilers,sram,verilog,timing,lef,

About UST
UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.

📌 Technical Lead I - VLSI (India)
🏢 UST
📍 India