strong RTL Design Verification engineers to perform block-level verification of IP components . The role involves validating functionality of IPs provided and ensuring readiness for SoC-level integration.
Key Responsibilities
Perform RTL design verification for IP blocks such as:
FSM (Finite State Machine)
DAC-related logic (with model interaction)
Pattern memory / controller logic
Develop and execute comprehensive verification plans
Build testbenches and verification environments (directed + random testing)
Validate functional correctness and interface behaviour
Perform debug and root cause analysis of RTL issues
Ensure coverage closure and verification completeness
Work closely with PD and integration teams to enable smooth SoC integration
Skill Requirements
Core Skills
Solid experience in RTL Design Verification
Positive understanding of:
Digital design fundamentals