Bangalore, KarnatakaChennai, Tamil Nadu
Job Summary

Experience with Cadence APD IC Package/substrate Design experienceGood experience with Flip Chip and Wire Bond designsWorked from Die pin list to Tape outGood understanding of package fabrication and assembly rules related to flip chip designs.Exposure to different package technologies such as MCM, flip chip / wire bond, 3D, 2.5D etc., added advantageShould have experience in working with High-speed interfaces such as PCIe, LPDDRx, GDDR, XGMII, etc.,Valuable knowledge and understanding in Signal Integrity and Power Integrity requirementsShould be able to work with customer SPOC independently.Valuable Exposure to Stackup design, DFM, DFA rules and adherence.Experience with Cadence APD IC Package/substrate Design experience

Key Responsibilities





Signal Integrity toolExpertSpecifically, in Cadence Sigrity 2.5D and 3D-EM and Agilent ADS.Power Integrity toolExpertSpecifically, in Cadence Sigrity 2.5D and 3D-EM and Hspice.Allegro toolKnowledgeBasic knowledge in Viewing/Understanding the routing details and extracting quick reports.Lab measurement equipmentGoodFamiliarity with Vector Network Analyzer (VNA) and Oscilloscopes.
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📌 Design Lead Bengaluru (India)
🏢 HCLTech
📍 India