Experience
4+ Years
Education
Bachelor's Degree (B.E./B.Tech) or Master's Degree (M.E./M.Tech/MS) in Electronics, Electrical Engineering, VLSI, Semiconductor Engineering, or related fields.
Notice Period
Immediate Joiners to 45 Days
Job Summary
We are looking for highly skilled DFT Engineers with robust expertise in Scan, ATPG, MBIST, and DFT architecture development for advanced SoC designs. The ideal candidate should have hands-on experience with Synopsys DFT tools and a proven track record in improving test coverage, implementing advanced test methodologies, and driving DFT signoff activities.
Key Responsibilities
Define and implement DFT architecture for complex SoC designs.
Perform synthesis and scan insertion using Synopsys tools.
Implement and optimize scan compression techniques to improve test efficiency.
Develop and integrate Streamline Fabric solutions.
Execute IJTAG (IEEE 1687) insertion and validation.
Implement and validate MBIST/SMS (Shared Memory System) architectures.
Perform memory repair and redundancy analysis where applicable.
Generate ATPG patterns and perform fault simulation for Stuck-at, Transition, and other fault models.
Debug and execute Gate-Level Simulations (GLS).
Perform Formality and Logical Equivalence Check (LEC) signoff.
Analyze test coverage and drive improvements in DFT quality metrics.
Collaborate with RTL, Verification, Physical Design, and Product Engineering teams to resolve DFT-related issues.
Drive DFT signoff and support silicon bring-up activities.
Pay: ₹500,000.00 - ₹3,500,000.00 per year
Work Location: In person
📌 DT Engineer (India)
🏢 VEDAMSEMI
📍 India
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