Key Responsibilities
Develop and execute comprehensive verification plans based on design specifications
Build and maintain SystemVerilog/UVM-based verification environments
Create reusable testbenches, agents, scoreboards, and checkers
Develop directed and constrained-random testcases
Perform functional, code, and assertion coverage closure
Debug failures and root-cause issues across RTL, testbench, and tools
Develop and integrate assertions (SVA) and formal checks where applicable
RTL as well as Gate level simulations
Automate regression flows and improve verification productivity

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Required Skills & Qualifications

Technical Skills
Strong expertise in SystemVerilog
Hands-on experience with UVM (Universal Verification Methodology)
Experience with functional coverage, assertions (SVA), and constrained random verification




Familiarity with EDA tools (e.g., VCS, Verdi)
Experience in debugging RTL and simulation issues
Understanding of protocols such as AXI, AHB, APB, PCIe, or similar

Programming/Scripting
Proficiency in Python/Perl/Shell scripting for automation

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Preferred Qualifications
Experience in UCIe protocol
Experience in verifying mixed signal (analog + digital) IPs

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Education
B.Tech / M.Tech in Electronics / Electrical / Computer Engineering or equivalent

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Soft Skills
Robust analytical and debugging skills
Positive communication and cross-functional collaboration
Ability to work in a rapid-paced, tapeout-driven environment

📌 Design And Verification Engineer Telangana (India)
🏢 HCLTech
📍 India