Job Description Hiring for: A leading global IT Services & Consulting firm (Top 5 in India)
n Experience: 7 years to 14 years
n Location: Bangalore
n Work Mode: Hybrid
n Notice Period: Immediate to 60Days
n Mandatory Skills
n n Design for Test
n (DFT)Scan Compression
n Automatic Test Pattern Generation
n (ATPG)Silicon Validation
n n Roles & Responsibilities
n n Develop and implement DFT architecture for complex SoC/ASIC designs.
n Design and integrate scan chains, scan compression, and boundary scan (JTAG) features.
n Generate and validate ATPG patterns for stuck-at, transition, and other fault models.
n Perform DFT verification, coverage analysis, and debug to achieve high manufacturing test coverage.
n Collaborate with RTL, Design, Physical Design, and Verification teams to ensure seamless DFT implementation.
n Support silicon bring-up, silicon validation, and production test activities issues.




n Analyze silicon test failures and work with cross-functional teams to identify and resolve
n Optimize DFT methodologies to improve test quality, reduce test time, and minimize test costs.
n Ensure compliance with industry-standard DFT methodologies and best practices.
n Prepare and maintain DFT documentation, test plans, and implementation reports.
n n Preferred Qualifications
n n Solid understanding of SoC/ASIC design flow.
n Experience with scan insertion, scan compression, ATPG, and fault coverage analysis.
n Hands-on experience in silicon validation and post-silicon debug
n Excellent debugging, analytical, and problem-solving skills.
n Robust communication and collaboration abilities.
n n Interested candidates, please share your updated resume to

📌 Design For Test Engineer Dft Bengaluru
🏢 Taggd
📍 Bengaluru