Lead Verification Engineer

Experience: 7+ years
Location: Hyderabad

Job Description:
Work as a member of a geographically distributed verification team to verify next-generation ASIC and FPGAs
Develop testplans, implement testbenches, create testcases, and ensure functional coverage closure
Handle regression testing and contribute to verification infrastructure development
Develop both directed and random verification tests
Debug test failures, identify root causes, and work with RTL and firmware engineers to resolve design defects and test issues
Review functional and code coverage metrics, modify or add tests or constrain random tests to meet coverage requirement
Collaborate with design, software and architecture teams to verify design under test

Preferred Experience:
Proficient in IP-level FPGA and ASIC verification
Knowledge of PCIe, CXL or other IO protocol is preferred
Proficient in Verilog/SystemVerilog,



and scripting languages such as Perl or Python
Hands-on experience with SystemVerilog and UVM is mandatory
Experience in developing UVM-based verification testbenches, processes, and flows
Solid understanding of design flow, verification methodology, and general computational logic design and verification

About Company
ACL Digital, a leader in digital engineering and transformation, is part of the ALTEN Group. At ACL Digital, we empower organizations to thrive in an AI-first world. Our expertise spans the entire technology stack, seamlessly integrating AI and data-driven solutions from Chip to cloud. By choosing ACL Digital, you gain a strategic advantage in navigating the complexities of digital transformation. Let us be your trusted partner in shaping the future.

📌 Verification Lead Hyderabad
🏢 ACL Digital
📍 Hyderabad