Job Location: Bangalore, India (This position requires a full-time, in office presence in our Bangalore, India office)
Job ID: AI2505
Job Description:
Areas of Focus and Key Responsibilities:
Exposure to High level SOC DFT architecture understanding including SCAN, MBIST, IP tests, JTAG.
Verification of the pre-SCAN and MBIST module integration as per specification
Module level verification of the SCAN and any other DFT module as per requirement
Verifying the DFD interfaces and features at full chip - IEEE 1500, IEEE1687, test data register (TDR) integrity.
Verifying the MBIST feature at the full chip to make sure a tool inserted RTL is integrated to the system is bug free.
Supporting the post-silicon validation by porting ATE test porting as well as the test that helps full chip post-si characterization.
Minimum Requirements:
Experience in complex SOC level
BSEE or MSEE with at least 10+ years of DFT DV experience on high complexity SoC designs.
Strong HDL programming skills Verilog, System Verilog and UVM with hands-on experience building from the scratch.
Must possess good communication skills, be a self-driven individual and a valuable team player.
Write scripts in TCL, Python and Perl to achieve productivity enhancements through automation.
Personal Attributes:
Can do attitude, execution and results focus, highly accountable, solid team player, high integrity, visionary, and innovative. Capable of handling difficult conversations in a professional manner.