Role description

Required Skills 5+ years of experience in Memory Layout or Custom Layout Design. Hands-on experience with SRAM, ROM, CAM, Register Files, or Memory Compiler layouts. Strong expertise in Cadence Virtuoso. Valuable knowledge of Calibre DRC, LVS, ERC, and DFM. Experience with advanced technology nodes (28nm, 16nm, 7nm, 5nm, or below). Understanding of layout effects, EM/IR, latch-up, antenna, and reliability concepts. Scripting knowledge in SKILL, Perl, Tcl, or Python is an added advantage. Excellent debugging, analytical, and problem-solving skills. Preferred Qualifications

Skills

Analog Layout, LVS, SRAM, Python

About UST
UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.

📌 Technical Lead I - VLSI ML BD (India)
🏢 UST
📍 India