Job Summary

We are looking for an experienced Design Verification Engineer with strong expertise in DDR5/LPDDR5 memory protocol verification for complex ASIC/SoC designs. The ideal candidate should have hands-on experience in SystemVerilog, UVM, and memory subsystem verification, with a minimum of 3 years of DDR/LPDDR verification experience. You will work closely with Design, Architecture, and Validation teams to develop robust verification environments, validate memory controller functionality, and ensure first-pass silicon success.

Key Responsibilities

- Verify DDR5/LPDDR5 memory controller and subsystem designs using SystemVerilog and UVM.
- Develop reusable UVM-based verification environments, testbenches, and verification components.
- Create directed and constrained-random test cases for functional verification.
- Develop verification plans, coverage models, and assertions to ensure comprehensive protocol validation.
- Debug RTL, test bench, and simulation failures to identify root causes.
- Execute regression suites and analyze functional coverage to achieve verification closure.
- Collaborate with Design, Architecture, and Physical Design teams to resolve verification issues.
- Participate in design reviews and contribute to verification methodology improvements.





Required Skills

- 7–10 years of experience in ASIC/SoC Design Verification.
- Minimum 3 years of hands-on experience in DDR/LPDDR memory protocol verification.
- Robust expertise in DDR5 and LPDDR5 protocols.
- Excellent programming skills in SystemVerilog (SV).
- Strong hands-on experience with UVM (Universal Verification Methodology).
- Experience in developing reusable verification environments and constrained-random verification.
- Strong debugging skills for RTL, protocol, and simulation issues.
- Experience with functional coverage, assertions, and regression execution.
- Good understanding of ASIC/SoC verification methodologies.

Preferred Skills

- Experience leading verification teams or owning verification projects.
- Familiarity with industry-standard EDA tools such as Synopsys VCS, Cadence Xcelium, or Verdi.
- Knowledge of additional verification methodologies and automation frameworks.
- Experience with scripting using Python, Perl, or Shell.
- Strong analytical and problem-solving skills.
- Excellent communication and interpersonal skills.

Pay: ₹1,400,000.00 - ₹2,000,000.00 per year

Work Location: In person

📌 Design Verification Engineer –/ LPSystemVerilog | UVM (Bengaluru)
🏢 Spatial Alphabet
📍 Bengaluru