Role description

Key requirements include:

- Hands-on experience in scan insertion, JTAG, ATPG DRC, and coverage analysis
- Proficiency in simulation debug with timing/SDF
- Experience with LBIST and Mixed Signal Radar ICs is highly desirable
- Ability to debug and root cause simulation failures
- Must be proactive, collaborative, and detail-oriented, capable of exercising independent judgment
- Strong interpersonal and communication skills (both oral and written)
- Self-motivated and adaptable

Skills

vlsi design,jtag,scan insertion,simulation debug,coverage analysis,timing analysis

About UST
UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.

📌 Associate III - VLSI DFT Engineer (India)
🏢 UST
📍 India