This role is for one of the Weekday's clients

Min Experience: 4+ years

Location: Bengaluru
Job Type: full-time

We are looking for an experienced Memory Layout Engineer with strong expertise in full-custom memory layout design. The ideal candidate should have hands-on experience in SRAM memory compiler development, memory array layouts, and physical verification while delivering high-quality layouts optimized for Performance, Power, and Area (PPA).

Requirements

Key Responsibilities

- Design and develop full-custom layouts for SRAM memory compiler blocks.
- Work on Memory Arrays, Bit Cells, Row Decoders, Column Decoders, Sense Amplifiers, Pre-charge Circuits, Write Drivers, I/O Circuits, and Control Blocks.
- Perform transistor-level placement and routing following advanced layout techniques.
- Optimize layouts for area, speed, power consumption, reliability, and manufacturability.
- Execute physical verification including DRC, LVS, ERC, Antenna, Latch-up, Density, and DFM checks.
- Debug layout issues and ensure clean sign-off.




- Collaborate closely with Circuit Design, Verification, Process, and Technology teams.
- Support top-level memory integration and compiler development.
- Ensure timely delivery while maintaining high-quality layout standards.
- Mentor junior engineers and participate in layout reviews (for senior candidates).

Mandatory Skills

- 4–8 years of experience in Memory Layout Design.
- Strong experience in SRAM Memory Compiler Layout.
- Hands-on experience in:
- Memory Arrays
- Bit Cell Layout
- Row & Column Decoders
- Sense Amplifiers
- Write Drivers
- Pre-charge Circuits
- Control Logic
- I/O Blocks

- Excellent knowledge of layout optimization for PPA.
- Solid understanding of matching, symmetry, shielding, and routing techniques.
- Expertise in physical verification:

- DRC
- LVS
- ERC
- Antenna
- Density Checks
- Latch-up

- Experience with advanced technology nodes (FinFET/CMOS preferred).

📌 Memory Layout Engineer (Bengaluru)
🏢 Weekday AI
📍 Bengaluru