Ø Atleast 8 years of relevant experience in the semiconductors industry (DfT, IC design and Verification).

Ø Experience in Analog DfT is a plus.

Ø Be fluent with all common concepts of DfT and DfT tools.

Ø Bring in some unique expertise

3

Educational Qualification

B.E or M.Tech in Electronics, Electrical, VLSI

4

Skills & Knowledge

Ø Robust knowledge and experience in Scan Insertion, TestKompression, ATPG, Memory BIST and JTAG at IC –level for mixed signal designs.

Ø Experience in using Mentor DfT tools, Cadence RC and simulator toolsexperience is a plus.

Ø Define DfT Strategy and Requirement Specification for the design.

Ø DfT verification for gate-level and timing simulations.

Ø Work cross sites with design team to define and implement DfT.

Ø Hands on experience in solving DfT problems, simulation failures, ATPG coverage and DRC improvements.

Ø Work with STA engineer to define timing constraints for DfT modes.

Ø Support Test engineer in silicon debug and pattern delivery for ATE.

Ø Experienced in handling analog DfT simulations.

Ø Experience in RTL coding, shell scripting.

Ø Experience in using version control tools like SVN.

📌 Senior Design Engineer (India)
🏢 Chiptest
📍 India