- Experience with the design and implementation of test methodologies for large, complex SoCs.
- Capable of resolving scan issue in complex multi-clock domain designs, developing DFT strategies for complex System-On-Chip designs, generate & integrate Memory BIST, JTAG, SCAN/ATPG.
- Expert in analysis of fault coverage, delay fault, and enhancements.
- Experience in developing and running scan insertion scripts, performing ATPG simulation & analyzing results.
- Expertise in Mentor / Synopsys DFT tools and debug skills in a Verilog design workplace.
- Experience with static timing analysis (STA) & formal verification is desirable.
- Proficiency in common UNIX scripting languages (perl, tcl, csh, sh).
- Email your resume to
[email protected] with Job Code – DFT in the subject line.
📌 Design For Test (India)
🏢 Perfectus Technology
📍 India