Role description

The 4-person team collectively should demonstrate:

- Create Subsystem Verification plan for PMBUS, AVS interface and sign off protocol compliance
- Formal verification coverage of critical control interfaces
- UVM based Verification setting
- SOC Integration verification and system level scenarios development
- GLS Verification including root causing down to flop level
- Code Coverage, functional coverage
- Fault Injection Campaign Execution for ASIL-D Products

Mandatory:

- Demonstration of AI-driven productivity improvements in Verification test case generation and coverage closure
- Should have thrived in fast paced environments ( startup like) in the recent past
- In Depth debug and Root cause analysis skills

Skills

vlsi design,protocol compliance,soc integration,ai-driven productivity improvement,





About UST
UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.

📌 Associate III - VLSI (India)
🏢 UST
📍 India