- Bachelor's / Master's degree in engineering from EEE / E&C; with expertise in RTL Design and SystemC based modeling for complex SoCs
- Expertise in developing and maintaining System C / TLM-2.0 models for SoC and IP subsystems
- Expertise in building cycle-accurate and transaction-level reference models for architectural exploration and functional validation
- Expertise in driving Model-RTL correlation and debug functional mismatches
- Expertise in collaborating with Architecture, RTL, and DV teams to define modeling requirements and validation strategies
- Expertise in developing validation frameworks, test scenarios, and automated regression flows
- Expertise in analyzing performance, latency, and corner cases to ensure model accuracy
- Expertise in enhancing modeling methodologies and automate flows using Python and scripting languages
- Expertise in supporting pre-silicon verification and early software enablement
- Expertise in Python, Shell scripting, and Linux development environments
- Expertise in working with virtual platforms and performance modeling is desirable
- Expertise in System Verilog, UVM, and simulation / debug environments
- Proven track record of delivering robust models and supporting first-pass silicon success.
- Valuable understanding of Design Verification methodologies and Model-RTL correlation.
- Knowledge of computer architecture, memory subsystems, and interconnect protocols such as PCIe, AXI, DDR, Ethernet, or NoC