4. Capable of creating test bench environment from scratch.
5. Capable of creating sequence as per requirement.
6. Capable of creating assertion & functional coverage.
7. Strong knowledge of APB / I2C / I3C Protocol.
Job Description :
We are looking for a motivated Verification Engineer with a strong understanding of System Verilog (SV) and UVM methodologies. This is an excellent prospect for a quick learner who is passionate about creating test plans and building testbench environments from scratch. You will work closely with our team to verify and validate digital designs, ensuring they meet the required functionality and performance standards.
Salary : Open to discussion
📌 Verification EngineerC_MASTER) (India)
🏢 MAXVY
📍 India
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