B.Tech or M.Tech in Electronics/Electrical Engineering with minimum of 6 years of robust, hands on Physical Design experience. Must have hands in hierarchical partitioning of internal hard macros/blocks from either chip top or sub system. Should have experience in 28nm & below technologies experience in 10nm & below is an added advantage

Skills Required

- hierarchical partitioning of internal hard macros/blocks from either chip top or sub system
- Top level die size estimation, floor planning, power estimation , power planning .
- Handling of PLL, TXR, DDR and other analog components during implementation.
- Scripting experience in Perl/TCL.
- Flow customization and fine tuning for Power , Performance, Area.
- Exposure to DFM and DFM compatible implementation.
- Excellent debugging skills in implementation issues and ability to come up with creative solutions .
- Exposure to designs critical for power, area and timing at the same time.
- Technologies from 28nm and below.
- Exposure to Physical design project planning and execution.
- Technical leadership and ability to mentor and make the team deliver.

Location: Bangalore, Hyderabad, Chennai and Delhi

send your resumes to [email protected]

📌 Floorplan lead (India)
🏢 The Nanopore Site
📍 India