- Responsible for PD Implementation of complex ASIC/SoCs
- Floorplan, Place & Route, SI Avoidance/fixing, power/clock distribution, timing closure - timing, power, clock and noise analysis and DRC/LVS
Job Requirements:
- 3-8 Years of Experience in Physical Design
- BE/BTECH/ME/MTECH in EC/EE/CS or related field
- Must have successful track record taping out complex chips (min 2M gates)
- Prior experience in design timing closure, Clock/Power distribution and analysis, RC Extraction, P & R
- Hands on experience in running STA & Synthesis
- Should be a power user of P&R; and analysis tools from Magma, Cadence or Synapses
- Coding experience in C++, C, Perl and TCL a big plus
📌 Physical Design (PD) Engineers (India)
🏢 intsemi
📍 India
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