Asic Rtl Engineer Iii, Silicon (Karnataka)

Asic Rtl Engineer Iii, Silicon (Karnataka)

03 Aug
|
Recognized
|
Karnataka

03 Aug

Recognized

Karnataka

Minimum qualifications Bachelor s degree in Electrical Engineering Computer Engineering Computer Science or a related field or equivalent practical experience 4 years of experience with digital logic design principles RTL design concepts and languages such as Verilog or SystemVerilog Experience with logic synthesis techniques to optimize RTL code performance and power as well as low-power design techniques Preferred qualifications Master s or PhD degree in Electrical Engineering Computer Engineering or Computer Science Experience with a scripting language like Perl or Python Experience with ASIC or FPGA design verification synthesis timing power analysis and DFT Knowledge of high-performance and low-power design techniques assertion-based formal verification FPGA and emulation platforms and SOC architecture Knowledge of memory compression fabric coherence cache or DRAM About the job Be part of a team that pushes boundaries developing custom silicon solutions that power the future of Google s direct-to-consumer products You ll contribute to the innovation behind products loved by millions worldwide Your expertise will shape the next generation of hardware experiences delivering unparalleled performance efficiency and integration The Platforms and Devices team encompasses Google s various computing software platforms across environments desktop mobile applications as well as our first party devices and services that combine the best of Google AI software and hardware Teams across this area research design and develop new technologies to make our user s interaction with computing faster and more seamless building innovative experiences for our users around the world Responsibilities Define the block-level design document e g interface protocol block diagram transaction flow pipeline etc Perform RTL coding function performance simulation debug and Lint Clock Domain Crossing CDC Formal Verification FV Unified Power Format UPF checks Participate in synthesis timing power closure and FPGA silicon bring-up Participate in test plan and coverage analysis of the block and ASIC-level verification Communicate and work with multi-disciplined and multi-site teams Google is proud to be an equal opportunity workplace and is an affirmative action employer We are committed to equal employment chance regardless of race color ancestry religion sex national origin sexual orientation age citizenship marital status disability gender identity or Veteran status We also consider qualified applicants regardless of criminal histories consistent with legal requirements See also Google s EEO Policy and EEO is the Law If you have a disability or special need that requires accommodation please let us know by completing our Accommodations for Applicants form

📌 Asic Rtl Engineer Iii, Silicon (Karnataka)
🏢 Recognized
📍 Karnataka

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