We are looking for profiles with 6-8 years experience in SoC RTL/DFx verification and debug, GLS simulations and debug, Verilog coding experience, good understanding on JTAG and verification in Testmode. It s valuable to have pattern generation and Silicon debug experience. Please let me know if you have suitable profiles.
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📌 Technical Lead I - VLSI (Karnataka)
🏢 UST
📍 Karnataka
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